Overview

Our research focuses on enhancing AI efficiency and applicability through balanced integration of algorithms and hardware using automated tools. We use a top-down approach for AI algorithm development and a bottom-up approach for hardware accelerators, aiming to bridge these perspectives with automated co-exploration and co-search techniques. Our goal is to maximize AI acceleration efficiency and speed up AI solution development.

  • Top-Down: Hardware-Aware Efficient AI/DNN Algorithms
    • We emphasize that AI algorithm design should account for the specific hardware capabilities of target devices. Key contributions include Early-Bird Tickets at ICLR'20 (spotlight paper, ranked top 3%), CPT-Train at ICLR'21 (spotlight paper, ranked top 3%), SuperTickets at ECCV'22, and ShiftAddLLM at NeurIPS'24.

  • Bottom-Up: Algorithm-Aware Efficient AI/DNN Accelerators
    • We focus on designing AI accelerators that go beyond conventional methods to leverage algorithmic opportunities. Notable works include SmartExchange at ISCA'20, ViTCoD at HPCA'23, Instant-3D at ISCA'23, and Gen-NeRF at ISCA'23.

  • Bridging: Automated Tools for Efficient AI Solutions
    • We develop automated tools to enhance efficiency and accelerate the creation of AI solutions. Key works include: AdaDeep at MobiSys'18, HW-NAS-Bench at ICLR'21 (spotlight paper, ranked top 3%), Auto-NBA at ICML'21, and GPT4AIGChip at ICCAD'23.

  • System Integration and Demonstration for Real-World Applications
  • i-FlatCam (ASIC):
    Won 1st Place in Best University Demo at DAC'2022
    A 253 FPS, 91.49 µJ/Frame
    Ultra-Compact Intelligent Lensless Camera
    Gen-NeRF (FPGA):
    Won 2nd Place in Best University Demo at DAC'2023
    Real-time, Low-power, and Generalizable Scene Rendering and Segmentation based on NeRFs with Interactive View Control